1. Field of the Invention
The present invention generally relates to methods of fabricating a semiconductor device and, more particularly, to methods of forming interconnect structures in a semiconductor device fabrication process.
2. Description of the Related Art
A process of fabricating a semiconductor integrated circuit is roughly divided into the process of forming devices on a silicon substrate and the process of electrically connecting the devices. The latter is called an interconnection process or metallization, and is a key for improving yield rate and reliability in the fabrication of semiconductor devices as the devices become more highly integrated.
A metal widely used as an interconnection material is aluminum (Al). However, as the integration of devices is improved, the interconnection line width is reduced, while its total length is increased, such that the signal transfer delay time, represented by the RC time constant, is lengthened. Furthermore, the reduction in interconnection line width results in cutting in the interconnection line due to electromigration or stress migration. Accordingly, in order to fabricate a reliable device with a fast operation speed, copper (Cu) is used instead of aluminum (Al) for forming the interconnection lines since it has lower resistance compared with that of Al and stronger resistance against electromigration and stress migration.
However, Cu lacks excellent properties that Al has other than the low resistance and high melting point. For example, Cu cannot form a dense protective layer such as Al2O3, has bad adhesive strength to SiO2 and is difficult to dry-etch. In addition, its diffusion coefficient in silicon is approximately 106 times larger than that of Al, and it is known that Cu diffused into the silicon forms a deep level between band gaps. Furthermore, copper's diffusion coefficient in SiO2 is known to be large, which decreases the ability of SiO2 to insulate between Cu lines. As a result of copper's large diffusion coefficient in silicon and SiO2, the reliability of the semiconductor device is reduced. Accordingly, to ensure the reliability of the device, a diffusion barrier capable of preventing Cu from rapidly diffusing into the silicon or SiO2 is required.
Ta or TaN thin films deposited by a sputtering process are currently being used as the diffusion barrier for Cu, instead of the TiN films generally used in the conventional Al interconnection line fabricating process. However, when the diffusion barrier is deposited in a contact or trench structure using sputtering, step coverage deteriorates as the device size becomes smaller. This problem suggests that it would be beneficial to form the diffusion barrier through a more conformal process, such as chemical vapor deposition (CVD).
However, the development of new processes for forming a reliable diffusion barrier for Cu requires a considerably long period of time and this may delay commercialization of a semiconductor device employing a Cu interconnect structure.
The present invention solves the above problems. It is an object of the present invention to provide methods for fabricating a semiconductor device employing a diffusion barrier whose grain boundary is stuffed with metal oxide, not a metal element constructing the diffusion barrier. This may advance commercialization of a semiconductor device with a Cu interconnect structure.